1. Field of the Invention
This invention generally relates to integrated circuit (IC) memory fabrication and, more particularly, to a metal/semiconductor/metal (MSM) binary switch memory device.
2. Description of the Related Art
A cross point memory array is a matrix of memory elements, with electrical contacts arranged along x-axes (i.e., word lines) and along y-axes (i.e., bit lines). In some aspects, a digital value is stored as a memory resistance (high or low). The memory state of a memory cell can read by supplying a voltage to the word line connected to the selected memory element. The resistance or memory state can be read as an output voltage of the bit line connected to the selected memory cell.
Cross point resistor memory arrays are prone to read disturbance problems. As part of the read operation, electric current flows from a selected word line, through a selected memory cell, to a bit line. However, current also flows into unselected word lines that happen to cross over the selected bit line. The conduction of current into unselected word lines acts to decrease the output impedance and, hence, reduce the output voltage. To clearly distinguish memory states, the output voltage must be clearly distinguishable.
The undesired flow of current through a resistance memory cell can be addressed through the use of series-connected diodes, since reverse biased diodes are poor conductors. However, this same feature makes a one-diode/one resistor (1D1R) memory difficult to program. Programming voltages cannot be used that reverse bias the diode. Therefore, 1D1R cells are better for suited for unipolar programming. Further, diodes are preferable formed from single crystal silicon, for optimal performance. However, large crystal grains are difficult to form using thin-film deposition processes.
Many cross point resistor memory array structures have been proposed in attempts to minimize cross-talk problems during read operations in a large area cross point resistor memory array. IRID memory cell are well suited for a mono-polarity programming memory array. However, good diodes can only be fabricated on single crystal silicon. For multi-layer three-dimensional arrays, the upper layer of a diode is formed by re-crystallization of deposited silicon, and the resulting diode usually exhibits poor electrical properties. In addition, the diode must be formed from a silicon film that is fairly thick.
Rinerson et al, U.S. Pat. No. 6,753,561, have proposed a memory cell of a metal/insulator/metal (MIM) structure in series with a resistor memory. The MIM device is non-conductive at low biases. When the bias voltage is higher than a certain value, the conductivity drastically increases. This voltage is called either the “current rise-up voltage” or “varistor voltage”. The high field generated in response to the MIM high current region is associated with impact ionization. As a result, the current voltage characteristics are reversible only at relatively low current conditions. The MIM device is unable to handle a large current density. In addition, Rinerson does not teach specific MIM materials, or how a MIM device is fabricated.
Current-sensing techniques have been used to better differentiate read memory signals in a large area array. However, current sensing requires a high-gain operational amplifier, which consumes relatively large areas of chip space.
It would be advantageous if the current flow through unselected lines in a cross point resistor memory cell array could be reduced, to maximize the bit line output voltage.
It would be advantageous if current flow through unselected lines could be reduced without the use of reverse biased diodes.